[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"article-iit-madras-dir-v-2026-chennai-semiconductor-en":3,"article-related-iit-madras-dir-v-2026-chennai-semiconductor-en":30,"series-industry-92e2685b-8bac-40ac-a7ad-bd8a571c0148":75},{"id":4,"slug":5,"title":6,"content":7,"summary":8,"source":9,"source_url":10,"author":11,"image_url":12,"cover_image":12,"category":13,"language":14,"translated_content":11,"related_article_id":15,"keywords":16,"key_takeaways":22,"views":26,"created_at":27,"published_at":28,"topic_cluster_id":29},"92e2685b-8bac-40ac-a7ad-bd8a571c0148","iit-madras-dir-v-2026-chennai-semiconductor-en","IIT Madras will host DIR-V 2026 in Chennai","\u003Cp data-speakable=\"summary\">IIT Madras will host DIR-V 2026 in Chennai on August 1-2.\u003C\u002Fp>\u003Cp>\u003Ca href=\"https:\u002F\u002Fwww.iitm.ac.in\" target=\"_blank\" rel=\"noopener\">IIT Madras\u003C\u002Fa> is bringing its third \u003Ca href=\"https:\u002F\u002Fwww.riscv.org\" target=\"_blank\" rel=\"noopener\">Digital India RISC-V\u003C\u002Fa> symposium to the \u003Ca href=\"https:\u002F\u002Fresearchpark.iitm.ac.in\" target=\"_blank\" rel=\"noopener\">IIT Madras Research Park\u003C\u002Fa> on August 1-2, 2026. The event is built around one blunt idea: India wants more control over the chips that power its digital economy, and open instruction-set design is part of that plan.\u003C\u002Fp>\u003Ctable>\u003Cthead>\u003Ctr>\u003Cth>Fact\u003C\u002Fth>\u003Cth>Detail\u003C\u002Fth>\u003C\u002Ftr>\u003C\u002Fthead>\u003Ctbody>\u003Ctr>\u003Ctd>Event\u003C\u002Ftd>\u003Ctd>Digital India RISC-V Symposium 2026\u003C\u002Ftd>\u003C\u002Ftr>\u003Ctr>\u003Ctd>Dates\u003C\u002Ftd>\u003Ctd>August 1-2, 2026\u003C\u002Ftd>\u003C\u002Ftr>\u003Ctr>\u003Ctd>Edition\u003C\u002Ftd>\u003Ctd>Third edition\u003C\u002Ftd>\u003C\u002Ftr>\u003Ctr>\u003Ctd>Venue\u003C\u002Ftd>\u003Ctd>IIT Madras Research Park, Chennai\u003C\u002Ftd>\u003C\u002Ftr>\u003Ctr>\u003Ctd>Theme\u003C\u002Ftd>\u003Ctd>Empowering Bharat’s Semiconductor Future\u003C\u002Ftd>\u003C\u002Ftr>\u003C\u002Ftbody>\u003C\u002Ftable>\u003Ch2>What IIT Madras is trying to build\u003C\u002Fh2>\u003Cp>The symposium is more than a conference with a chip-shaped theme. It is a meeting point for policymakers, researchers, startups, investors, faculty members, students, and industry leaders who are working on processor design, embedded systems, AI hardware, and \u003Ca href=\"\u002Ftag\u002Fcybersecurity\">cybersecurity\u003C\u002Fa>.\u003C\u002Fp>\n\u003Cfigure class=\"my-6\">\u003Cimg src=\"https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1784988186485-c192.png\" alt=\"IIT Madras will host DIR-V 2026 in Chennai\" class=\"rounded-xl w-full\" loading=\"lazy\" \u002F>\u003C\u002Ffigure>\n\u003Cp>That mix matters because semiconductor work in India has often been fragmented. Universities produce talent, startups prototype ideas, and government programs fund strategic capacity, but those groups do not always sit in the same room. DIR-V is trying to compress that distance.\u003C\u002Fp>\u003Cp>\u003Ca href=\"https:\u002F\u002Fwww.meity.gov.in\" target=\"_blank\" rel=\"noopener\">MeitY\u003C\u002Fa> is one of the partners, alongside \u003Ca href=\"https:\u002F\u002Fwww.riscv.org\" target=\"_blank\" rel=\"noopener\">RISC-V International\u003C\u002Fa>, which maintains the open-standard RISC-V instruction set architecture. For India, that matters because open standards lower dependence on a single vendor’s chip roadmap.\u003C\u002Fp>\u003Cul>\u003Cli>Third edition of the symposium\u003C\u002Fli>\u003Cli>Two-day format in Chennai\u003C\u002Fli>\u003Cli>Theme: “Empowering Bharat’s Semiconductor Future”\u003C\u002Fli>\u003Cli>Focus areas include processor design and AI hardware\u003C\u002Fli>\u003C\u002Ful>\u003Ch2>Why RISC-V keeps showing up in India’s chip plans\u003C\u002Fh2>\u003Cp>\u003Ca href=\"\u002Ftag\u002Frisc-v\">RISC-V\u003C\u002Fa> is an instruction set architecture, which is the rulebook a processor follows to execute code. Unlike proprietary architectures, it is open and extensible, which makes it attractive for research labs, startups, and national chip programs that want more design freedom.\u003C\u002Fp>\u003Cp>India has been talking for years about building deeper semiconductor capacity, but the real bottleneck is not just fabrication. It is design talent, toolchains, verification, system integration, and the ability to turn ideas into products. That is where an event like DIR-V can do practical work.\u003C\u002Fp>\u003Cblockquote>“As India’s digital economy expands, secure and trusted semiconductor technologies have become a strategic national priority,” said V. Kamakoti, Director of IIT Madras.\u003C\u002Fblockquote>\u003Cp>Kamakoti’s comment gets to the point better than any brochure could. India does not need chip talk for its own sake; it needs chips that can be designed, audited, adapted, and shipped in a way that fits local strategic needs.\u003C\u002Fp>\u003Cp>The symposium also gives startups and labs a stage for live demos. That is important because semiconductor conversations can get abstract fast. A working processor board, an embedded system demo, or a security prototype tells you more than a hundred slides about where a team actually is.\u003C\u002Fp>\u003Ch2>What the event says about India’s chip strategy\u003C\u002Fh2>\u003Cp>The guest list tells the story. When policymakers, global technology experts, and industry leaders gather around an open ISA, the discussion is no longer about whether India should care about chip design. It is about which parts of the stack India can influence now.\u003C\u002Fp>\n\u003Cfigure class=\"my-6\">\u003Cimg src=\"https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1784988185094-59dm.png\" alt=\"IIT Madras will host DIR-V 2026 in Chennai\" class=\"rounded-xl w-full\" loading=\"lazy\" \u002F>\u003C\u002Ffigure>\n\u003Cp>That stack includes architecture choices, IP reuse, verification, manufacturing partnerships, and the software that runs on top. RISC-V is useful here because it lets teams experiment without asking permission from a closed platform owner.\u003C\u002Fp>\u003Cul>\u003Cli>Open ISA: RISC-V\u003C\u002Fli>\u003Cli>Institutional host: IIT Madras\u003C\u002Fli>\u003Cli>Government partner: MeitY\u003C\u002Fli>\u003Cli>International standards body: RISC-V International\u003C\u002Fli>\u003Cli>Venue city: Chennai\u003C\u002Fli>\u003C\u002Ful>\u003Cp>There is also a talent angle that is easy to miss. Students and faculty members get direct exposure to the same people shaping India’s chip policy and product roadmaps. That kind of proximity can shorten the path from academic work to startup formation or industrial deployment.\u003C\u002Fp>\u003Cp>For readers tracking India’s broader tech policy, this symposium fits the same arc as other homegrown compute efforts, including processor research, secure hardware, and public-sector support for strategic technology. If you want a related read, see \u003Ca href=\"\u002Fnews\u002Findia-chip-design-push-open-standards\" target=\"_blank\" rel=\"noopener\">our coverage of India’s chip design push\u003C\u002Fa>.\u003C\u002Fp>\u003Ch2>What to watch on August 1-2\u003C\u002Fh2>\u003Cp>The most useful signals will not come from panel titles. They will come from the demos, the startup exhibits, and who shows up to talk about deployment rather than theory. If the event produces concrete collaborations between academia and industry, that will matter more than the usual event recap.\u003C\u002Fp>\u003Cp>It will also be worth watching whether the conversation stays centered on open silicon design, or broadens into procurement, manufacturing, and export-ready product paths. India has already shown it can host ambitious tech policy events; the harder part is turning them into repeatable execution.\u003C\u002Fp>\u003Cp>DIR-V 2026 gives India a rare chance to connect policy language with engineering reality. If the symposium produces even a handful of serious design partnerships, the bigger question becomes simple: which Indian chips will move from conference demo to commercial product first?\u003C\u002Fp>","IIT Madras will host DIR-V 2026 on August 1-2 in Chennai, putting India’s open-chip ambitions in one room.","www.thehindubusinessline.com","https:\u002F\u002Fwww.thehindubusinessline.com\u002Finfo-tech\u002Fiit-madras-to-host-digital-india-risc-v-symposium-2026-on-indias-semiconductor-future\u002Farticle71252695.ece\u002Famp\u002F",null,"https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1784988186485-c192.png","industry","en","bbf7567c-300c-4ba7-96ad-3a42d1ee1794",[17,18,19,20,21],"RISC-V","IIT Madras","semiconductors","MeitY","chip design",[23,24,25],"DIR-V 2026 will run on August 1-2 at IIT Madras Research Park in Chennai.","The symposium centers on open RISC-V design and India’s semiconductor ambitions.","Live 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