[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"tag-computex-2026":3},{"tag":4,"articles":10},{"id":5,"name":6,"slug":7,"article_count":8,"description_zh":9,"description_en":9},"d728f219-dfe5-4343-9eff-5c7f1acd2fc0","Computex 2026","computex-2026",0,null,[11],{"id":12,"slug":13,"title":14,"summary":15,"category":16,"image_url":17,"cover_image":17,"language":18,"created_at":19},"1b11c991-1388-4426-93e8-cc81e5cce5f9","5-reasons-risc-v-is-winning-new-chip-designs-en","5 reasons RISC-V is winning new chip designs","5 reasons RISC-V is moving from academia to standard status, as its CEO says it is becoming the default ISA for new chips.","industry","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1780657364895-h6zo.png","en","2026-06-05T11:02:21.081404+00:00"]