[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"tag-mips-s8200":3},{"tag":4,"articles":10},{"id":5,"name":6,"slug":7,"article_count":8,"description_zh":9,"description_en":9},"03ead577-4998-4643-896b-60fd92192eef","MIPS S8200","mips-s8200",0,null,[11],{"id":12,"slug":13,"title":14,"summary":15,"category":16,"image_url":17,"cover_image":17,"language":18,"created_at":19},"f9d8df2e-11f9-45cb-8924-b87d697db555","mips-risc-v-ai-ip-ces-edge-models-en","MIPS shows RISC-V AI IP for edge models at CES","MIPS unveiled S8200, a RISC-V AI processor IP block for edge models that targets tens to hundreds of TOPS and 2027 silicon.","model-release","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1780668185416-ropg.png","en","2026-06-05T14:02:33.198273+00:00"]