[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"tag-risc-v":3},{"tag":4,"articles":11,"peer_article_count":212},{"id":5,"name":6,"slug":7,"article_count":8,"description_zh":9,"description_en":10},"8444a70b-d5d5-4945-9392-c3ca6e854f91","RISC-V","risc-v",17,"RISC-V 是開放指令集架構，正從開發板延伸到 AI SBC、伺服器晶片與 Linux\u002FUbuntu 支援。它的重點在於降低授權門檻、加速客製化設計，也讓本地 AI、HPC 與嵌入式系統有更多硬體選擇。","RISC-V is an open instruction set architecture moving from hobby boards into AI SBCs, server-class chips, and mainstream Linux and Ubuntu support. It matters because it lowers licensing barriers and enables custom silicon for local AI, HPC, and embedded systems.",[12,21,29,36,43,50,57,64,71,78,85,92,99,106,113,120,127,135,142,149,156,163,170,177,184,191,198,205],{"id":13,"slug":14,"title":15,"summary":16,"category":17,"image_url":18,"cover_image":18,"language":19,"created_at":20},"cfb35ee3-0cf5-41e4-885e-1b38e3c9144e","spacemit-k3-riscv-mini-desktop-usably-quick-en","SpacemiT’s K3 makes RISC-V feel usable","4 ways SpacemiT’s K3 mini desktop shows RISC-V can run Ubuntu smoothly, but at a higher price.","industry","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1781176686850-dmcv.png","en","2026-06-11T11:17:26.353883+00:00",{"id":22,"slug":23,"title":24,"summary":25,"category":26,"image_url":27,"cover_image":27,"language":19,"created_at":28},"9a00bc96-0789-42fa-a107-f10eaf7b181d","vortex-3-0-risc-v-gpu-3d-pipeline-en","Vortex 3.0 turns RISC-V compute into a 3D GPU","Vortex 3.0 adds a 3D pipeline, Vulkan, and HIP support to Georgia Tech’s open-source RISC-V GPU stack.","tools","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1781175814346-3qpx.png","2026-06-11T11:03:01.355139+00:00",{"id":30,"slug":31,"title":32,"summary":33,"category":17,"image_url":34,"cover_image":34,"language":19,"created_at":35},"e57d8e32-a12b-45a9-bf9a-d58abecec3c0","fedora-44-risc-v-widens-linux-board-support-en","Fedora 44 RISC-V widens Linux board support","Fedora 44 RISC-V images add an Omni kernel that boots on 17 boards and broadens support beyond upstream-ready hardware.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1781025488724-g6ma.png","2026-06-09T17:17:24.883927+00:00",{"id":37,"slug":38,"title":39,"summary":40,"category":17,"image_url":41,"cover_image":41,"language":19,"created_at":42},"0b06b38d-9d52-465b-a32c-20658ec99f6e","how-to-set-up-spacemit-k3-risc-v-sbc-en","How to Set Up a SpacemiT K3 RISC-V SBC","Set up a SpacemiT K3 Pico-ITX SBC or K3-CoM260 SoM for boot, storage, networking, and OS testing.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1780844581027-qdr8.png","2026-06-07T15:02:30.18636+00:00",{"id":44,"slug":45,"title":46,"summary":47,"category":26,"image_url":48,"cover_image":48,"language":19,"created_at":49},"c52930db-c317-440e-8375-4c436e38b848","how-to-use-petros-ch32h417m-alef-board-en","How to use the Petros CH32H417M Alef board","Set up the Petros CH32H417M Alef as a Pico-sized RISC-V camera board.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1780663685207-99w8.png","2026-06-05T12:47:33.023332+00:00",{"id":51,"slug":52,"title":53,"summary":54,"category":17,"image_url":55,"cover_image":55,"language":19,"created_at":56},"a7b55f18-3fe1-4e94-8bd0-93138296223d","risc-v-gpu-pairing-right-soc-bet-en","Why RISC-V and GPU Pairing Is the Right SoC Bet","RISC-V SoCs win when they pair CPU, AI, and GPU into one software-ready platform.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1780659169249-lfph.png","2026-06-05T11:32:21.124697+00:00",{"id":58,"slug":59,"title":60,"summary":61,"category":17,"image_url":62,"cover_image":62,"language":19,"created_at":63},"bf79f668-be3c-4071-a737-1b7cf680d219","risc-v-news-chip-tracking-playbook-en","RISC-V news turns chip tracking into a playbook","I break down EE Times’ RISC-V tag page into a practical watchlist for AI, sovereignty, and chip design moves.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1780658303786-m9rj.png","2026-06-05T11:17:55.680026+00:00",{"id":65,"slug":66,"title":67,"summary":68,"category":17,"image_url":69,"cover_image":69,"language":19,"created_at":70},"1b11c991-1388-4426-93e8-cc81e5cce5f9","5-reasons-risc-v-is-winning-new-chip-designs-en","5 reasons RISC-V is winning new chip designs","5 reasons RISC-V is moving from academia to standard status, as its CEO says it is becoming the default ISA for new chips.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1780657364895-h6zo.png","2026-06-05T11:02:21.081404+00:00",{"id":72,"slug":73,"title":74,"summary":75,"category":17,"image_url":76,"cover_image":76,"language":19,"created_at":77},"683034bf-04fa-484e-b92f-79b21c048dec","why-bytedance-is-right-to-build-its-own-cpus-en","Why ByteDance Is Right to Build Its Own CPUs","ByteDance should build in-house CPUs to control cost, supply, and AI infrastructure performance.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1780305472253-bspg.png","2026-06-01T09:17:20.516159+00:00",{"id":79,"slug":80,"title":81,"summary":82,"category":17,"image_url":83,"cover_image":83,"language":19,"created_at":84},"112f8435-0385-4fc8-acf7-660949f914c9","cea-list-risc-v-europe-summit-2026-playbook-en","CEA-List’s RISC-V booth turns Summit into a playbook","CEA-List’s Summit page turns one event listing into a practical RISC-V meetup and demo plan.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1780304630781-3jiw.png","2026-06-01T09:03:13.135821+00:00",{"id":86,"slug":87,"title":88,"summary":89,"category":17,"image_url":90,"cover_image":90,"language":19,"created_at":91},"a5a7782b-2c64-471a-ac8b-050ff0a3a8fb","alibaba-android-16-risc-v-chips-en","Alibaba runs Android 16 on RISC-V chips","Alibaba’s DAMO Academy says it has ported Android 16 to XuanTie RISC-V silicon, a first for RVA23 processors.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1780165081815-x0jr.png","2026-05-30T18:17:40.032841+00:00",{"id":93,"slug":94,"title":95,"summary":96,"category":17,"image_url":97,"cover_image":97,"language":19,"created_at":98},"e1ee9b72-a612-413d-967b-b25a75678601","5-reasons-bytedance-is-building-custom-cpus-en","5 reasons ByteDance is building custom CPUs","5 reasons ByteDance is building custom CPUs for AI data centers, from rising Intel and AMD prices to export controls and Arm vs RISC-V bets.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1780164171283-z9im.png","2026-05-30T18:02:24.667234+00:00",{"id":100,"slug":101,"title":102,"summary":103,"category":26,"image_url":104,"cover_image":104,"language":19,"created_at":105},"c51b3f35-eaa8-42b4-8671-9393f3225291","how-to-evaluate-firefly-csc2-n48spk3-risc-v-server-en","How to Evaluate Firefly CSC2-N48SPK3","Evaluate Firefly’s 48-node RISC-V AI server and its software fit before buying.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1779732959631-6d9n.png","2026-05-25T18:15:36.374893+00:00",{"id":107,"slug":108,"title":109,"summary":110,"category":26,"image_url":111,"cover_image":111,"language":19,"created_at":112},"32ead109-f017-42b4-a14c-9569168a984e","risc-v-router-crowdfunding-e-ink-kit-windows-11-en","RISC-V router crowdfunding, E Ink kit, Windows 11 taskbar","Start9 is crowdfunding a $300 RISC-V Wi‑Fi router, M5Stack launched a $75 E Ink color dev kit, and Windows 11 taskbar tweaks are back for Insiders.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1779362769059-tz2g.png","2026-05-21T11:25:35.157988+00:00",{"id":114,"slug":115,"title":116,"summary":117,"category":26,"image_url":118,"cover_image":118,"language":19,"created_at":119},"f915d006-a80b-435e-a93c-a9a0b30dbd17","singnova-h-studio-local-ai-pc-risc-v-en","SingNova-H Studio turns local AI into a PC","SingNova-H Studio packs 200 TOPS into a local AI PC built around RISC-V dataflow design.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1779362176673-nfm3.png","2026-05-21T11:15:54.577829+00:00",{"id":121,"slug":122,"title":123,"summary":124,"category":17,"image_url":125,"cover_image":125,"language":19,"created_at":126},"342f03ea-5b21-4fdb-8bcb-ae75c6be3a2a","5-risc-v-basics-for-builders-en","5 RISC-V basics for builders","5 RISC-V basics explain the open ISA, its extensions, and why chips from MCUs to servers now use it.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1779361569517-1iaf.png","2026-05-21T11:05:39.535169+00:00",{"id":128,"slug":129,"title":130,"summary":131,"category":132,"image_url":133,"cover_image":133,"language":19,"created_at":134},"8b0922ab-5453-4b2f-9cf7-4937d844521a","sifive-third-gen-p550-p570-risc-v-cores-en","SiFive launches third-gen P550 and P570 cores","SiFive launched third-generation P550 and P570 RISC-V cores, led by the P570 Gen 3 out-of-order core for high-performance designs.","model-release","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1779150237628-fvn0.png","2026-05-19T00:23:35.137378+00:00",{"id":136,"slug":137,"title":138,"summary":139,"category":17,"image_url":140,"cover_image":140,"language":19,"created_at":141},"5fa9090a-3b4a-4d7c-8e16-3b18ef406a42","sifive-p570-gen3-rva23-platform-core-en","Why SiFive’s P570 Gen3 matters more as a platform than a core","SiFive’s P570 Gen3 is important because RVA23 support turns RISC-V into a serious mainstream platform.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1778994229185-yar4.png","2026-05-17T05:03:24.957589+00:00",{"id":143,"slug":144,"title":145,"summary":146,"category":17,"image_url":147,"cover_image":147,"language":19,"created_at":148},"5f8c17a6-6c8f-4db9-997e-24bbc6166716","hightec-sifive-safety-critical-risc-v-development-en","Why HighTec and SiFive are right to push safety-critical RISC-V","HighTec and SiFive are right: safety-critical automotive and industrial software needs qualified RISC-V toolchains, not more proprietary lock-in.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1778425846175-p0od.png","2026-05-10T15:10:25.064771+00:00",{"id":150,"slug":151,"title":152,"summary":153,"category":17,"image_url":154,"cover_image":154,"language":19,"created_at":155},"cff0f03f-8419-410d-a2f2-8b2e0b89a93e","why-banana-pi-risc-v-edge-ai-board-matters-en","Why Banana Pi’s RISC-V edge AI board matters","Banana Pi’s BPI-SM10 shows RISC-V is ready for serious local AI hardware.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1777969864596-qu0p.png","2026-05-05T08:30:37.056245+00:00",{"id":157,"slug":158,"title":159,"summary":160,"category":26,"image_url":161,"cover_image":161,"language":19,"created_at":162},"38bfb247-860f-4044-83ea-0964a269e2a1","banana-pi-bpi-sm10-risc-v-ai-sbc-en","Banana Pi BPI-SM10: RISC-V Board for Local AI","Banana Pi’s BPI-SM10 pairs a RISC-V chip with up to 60 TOPS for local AI, plus USB 3.0, Gigabit Ethernet, and M.2 slots.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1777639252479-p6cz.png","2026-05-01T12:40:35.808767+00:00",{"id":164,"slug":165,"title":166,"summary":167,"category":17,"image_url":168,"cover_image":168,"language":19,"created_at":169},"c3a5c73d-8ac2-4f0d-8554-49a13919a5a6","calligo-raises-12-15-million-risc-v-chip-push-en","$12-15 million for Calligo’s RISC-V chip push","Calligo Technologies is seeking $12-15 million, led by BIG Capital, to scale its indigenous RISC-V chips for AI and HPC markets.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1777638652609-hxju.png","2026-05-01T12:30:31.514468+00:00",{"id":171,"slug":172,"title":173,"summary":174,"category":17,"image_url":175,"cover_image":175,"language":19,"created_at":176},"0b5b7804-ce6a-4fe1-92fd-fcbeef8f5f9d","canonical-ubuntu-risc-v-2026-desktop-server-en","Canonical Bets on Ubuntu for RISC-V in 2026","Canonical says 2026 will be the year RISC-V moves from pilots to commercial Ubuntu systems, including desktop and server hardware.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1775272196612-525w.png","2026-04-04T03:09:33.125053+00:00",{"id":178,"slug":179,"title":180,"summary":181,"category":17,"image_url":182,"cover_image":182,"language":19,"created_at":183},"f9ee5b22-b62c-4941-868e-7722b84b554b","alibaba-risc-v-ai-cpu-server-chips-en","Alibaba’s RISC-V AI CPU Pushes Into Server Chips","Alibaba’s 64-bit RISC-V CPU hits 3.2 GHz on TSMC 5nm, targets agentic AI, and challenges Arm and Apple-style server silicon.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1775197509113-we45.png","2026-04-03T06:24:45.325498+00:00",{"id":185,"slug":186,"title":187,"summary":188,"category":17,"image_url":189,"cover_image":189,"language":19,"created_at":190},"063ea8e9-ebc7-43ac-9f9e-061f5aaf52b9","china-riscv-achievements-open-source-chip-industry-en","China’s RISC-V push hits a new milestone","CAS says Xiangshan set a new record and Ruyi first supported RVA23, signaling a bigger push for open-source chips in China.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1775180033405-nimr.png","2026-04-03T01:33:30.816685+00:00",{"id":192,"slug":193,"title":194,"summary":195,"category":132,"image_url":196,"cover_image":196,"language":19,"created_at":197},"0d7fb12b-52c1-476e-8d17-ae10816464d2","esp32-s31-wifi-6-gigabit-ethernet-risc-v-en","Espressif’s ESP32-S31 packs Wi‑Fi 6 and Gigabit Ethernet","Espressif’s ESP32-S31 pairs dual RISC-V cores with Wi‑Fi 6, Bluetooth 5.4, 802.15.4, and Gigabit Ethernet in a single MCU.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1775179847171-jz8q.png","2026-04-03T01:30:31.748018+00:00",{"id":199,"slug":200,"title":201,"summary":202,"category":26,"image_url":203,"cover_image":203,"language":19,"created_at":204},"6b09d971-3ca8-4e5e-a6fa-9c176b5b4892","rise-free-risc-v-github-runners-en","RISE Adds Free RISC-V GitHub Runners","RISE now offers free GitHub Runners on real RISC-V hardware, removing a major CI barrier for open source projects.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1775179665803-38vj.png","2026-04-03T01:27:27.818832+00:00",{"id":206,"slug":207,"title":208,"summary":209,"category":17,"image_url":210,"cover_image":210,"language":19,"created_at":211},"ba4d8580-aa49-4ade-8016-578a12e7794f","rvcc-llvm-incubator-riscv-optimizations-en","RVCC Wants Faster RISC-V Tuning in LLVM","RVCC is being proposed as an LLVM incubator to speed up RISC-V compiler tuning, but LLVM maintainer Nikita Popov already objects.","https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1775179487144-likv.png","2026-04-03T01:24:25.94061+00:00",29]