[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"article-sifive-third-gen-p550-p570-risc-v-cores-zh":3,"article-related-sifive-third-gen-p550-p570-risc-v-cores-zh":33,"series-model-release-24f4fceb-5a3c-4b7f-bfd4-611c7d63b439":85},{"id":4,"slug":5,"title":6,"content":7,"summary":8,"source":9,"source_url":10,"author":11,"image_url":12,"cover_image":12,"category":13,"language":14,"translated_content":11,"related_article_id":15,"keywords":16,"key_takeaways":25,"views":29,"created_at":30,"published_at":31,"topic_cluster_id":32},"24f4fceb-5a3c-4b7f-bfd4-611c7d63b439","sifive-third-gen-p550-p570-risc-v-cores-zh","SiFive 推出第三代 P550 與 P570 核心","\u003Cp data-speakable=\"summary\">SiFive 推出第三代 P550 與 P570 \u003Ca href=\"\u002Ftag\u002Frisc-v\">RISC-V\u003C\u002Fa> 核心，主打高效能晶片設計。\u003C\u002Fp>\u003Cp>說真的，這消息不只是在換版本號。\u003Ca href=\"https:\u002F\u002Fwww.sifive.com\" target=\"_blank\" rel=\"noopener\">SiFive\u003C\u002Fa> 把 \u003Ca href=\"https:\u002F\u002Fwww.sifive.com\u002Fcores\u002Fperformance\" target=\"_blank\" rel=\"noopener\">Performance P550\u003C\u002Fa> 和 \u003Ca href=\"https:\u002F\u002Fwww.sifive.com\u002Fcores\u002Fperformance\" target=\"_blank\" rel=\"noopener\">Performance P570\u003C\u002Fa> 推進到第三代。它想證明，\u003Ca href=\"https:\u002F\u002Friscv.org\" target=\"_blank\" rel=\"noopener\">RISC-V\u003C\u002Fa> 不只適合微控制器，也能碰高階 CPU 設計。\u003C\u002Fp>\u003Cp>這次最有看頭的是 \u003Ca href=\"https:\u002F\u002Fwww.sifive.com\u002Fcores\u002Fperformance\" target=\"_blank\" rel=\"noopener\">P570 Gen 3\u003C\u002Fa>。SiFive 直接把它描述成同級裡最強、也最有效率的 out-\u003Ca href=\"\u002Fnews\u002F5-compliance-uses-for-microsoft-365-copilot-zh\">of\u003C\u002Fa>-order 核心。講白了，就是它想跟 ARM、x86 這些老面孔正面搶設計案。\u003C\u002Fp>\u003Ctable>\u003Cthead>\u003Ctr>\u003Cth>項目\u003C\u002Fth>\u003Cth>公開資訊\u003C\u002Fth>\u003Cth>意義\u003C\u002Fth>\u003C\u002Ftr>\u003C\u002Fthead>\u003Ctbody>\u003Ctr>\u003Ctd>P550 Gen 3\u003C\u002Ftd>\u003Ctd>第三代 Performance 核心\u003C\u002Ftd>\u003Ctd>瞄準更高效能的通用運算\u003C\u002Ftd>\u003C\u002Ftr>\u003Ctr>\u003Ctd>P570 Gen 3\u003C\u002Ftd>\u003Ctd>同級最強、最有效率的 out-of-order 核心\u003C\u002Ftd>\u003Ctd>鎖定高階 CPU 工作負載\u003C\u002Ftd>\u003C\u002Ftr>\u003Ctr>\u003Ctd>發表地點\u003C\u002Ftd>\u003Ctd>Santa Clara, California\u003C\u002Ftd>\u003Ctd>顯示這是面向晶片設計商的 IP 發表\u003C\u002Ftd>\u003C\u002Ftr>\u003C\u002Ftbody>\u003C\u002Ftable>\u003Ch2>SiFive 這次到底講了什麼\u003C\u002Fh2>\u003Cp>先講結論。這次公告沒有丟完整 benchmark。它給的是方向，不是滿分考卷。官方重點放在第三代 Performance IP、out-of-order 執行、效率和持續效能。\u003C\u002Fp>\n\u003Cfigure class=\"my-6\">\u003Cimg src=\"https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1779150236307-rv7h.png\" alt=\"SiFive 推出第三代 P550 與 P570 核心\" class=\"rounded-xl w-full\" loading=\"lazy\" \u002F>\u003C\u002Ffigure>\n\u003Cp>對晶片團隊來說，這種更新很實際。CPU 核心一換代，功耗預算、面積、快取配置都會跟著變。你做的是 SoC，不是海報，所以這些細節比文案重要多了。\u003C\u002Fp>\u003Cp>如果你在做伺服器、邊緣運算，或想把 \u003Ca href=\"\u002Fnews\u002Fvatican-ai-brief-copyable-zh\">AI\u003C\u002Fa> 推論塞進自家晶片，核心選擇就很敏感。差一點點效能，可能就是能不能把散熱壓住。差一點點面積，可能就是成本直接跳一級。\u003C\u002Fp>\u003Cul>\u003Cli>新核心是 \u003Ca href=\"https:\u002F\u002Fwww.sifive.com\u002Fcores\u002Fperformance\" target=\"_blank\" rel=\"noopener\">P550 Gen 3\u003C\u002Fa> 和 \u003Ca href=\"https:\u002F\u002Fwww.sifive.com\u002Fcores\u002Fperformance\" target=\"_blank\" rel=\"noopener\">P570 Gen 3\u003C\u002Fa>。\u003C\u002Fli>\u003Cli>\u003Ca href=\"https:\u002F\u002Fwww.sifive.com\u002Fcores\u002Fperformance\" target=\"_blank\" rel=\"noopener\">P570 Gen 3\u003C\u002Fa> 被定位成同級最強、最有效率的 out-of-order 核心。\u003C\u002Fli>\u003Cli>這次發表來自 \u003Ca href=\"https:\u002F\u002Fwww.sifive.com\" target=\"_blank\" rel=\"noopener\">SiFive\u003C\u002Fa>。\u003C\u002Fli>\u003Cli>它主打的是 \u003Ca href=\"https:\u002F\u002Friscv.org\" target=\"_blank\" rel=\"noopener\">RISC-V\u003C\u002Fa> 的第三代高效能 IP。\u003C\u002Fli>\u003C\u002Ful>\u003Ch2>為什麼這對 RISC-V 很重要\u003C\u002Fh2>\u003Cp>RISC-V 一直有兩張臉。一張是開放、彈性、好客製。另一張是軟體成熟度和效能，常被拿來跟 ARM 比。這次 SiFive 往上推高效能核心，就是在回應後者的質疑。\u003C\u002Fp>\u003Cp>尤其是 out-of-order 核心。這類設計比 in-order 複雜很多。它要處理更多排程、預測和管線控制。工程難度高，功耗也更難壓。能把這類核心做穩，才有機會進更高階的產品。\u003C\u002Fp>\u003Cp>我覺得這點很現實。RISC-V 的問題從來不是「能不能做」。而是「做出來後，誰敢拿去量產」。SiFive 這次就是想把答案往前推一格。\u003C\u002Fp>\u003Cblockquote>“RISC-V is the first open standard instruction set architecture that is not tied to a single company or country,” said Krste Asanović, professor at UC Berkeley and a founder of the RISC-V project.\u003C\u002Fblockquote>\u003Cp>這句話很直白，也很關鍵。RISC-V 的價值不只在技術。它還牽涉到授權、供應鏈和長期控制權。很多公司想要的是 CPU 路線自己說了算。\u003C\u002Fp>\u003Cp>SiFive 賣的不是單一核心而已。它賣的是一條比較自由的晶片路線。對想做自有 SoC 的廠商來說，這件事很有吸引力。\u003C\u002Fp>\u003Ch2>跟市場比，SiFive 站在哪裡\u003C\u002Fh2>\u003Cp>SiFive 不是唯一做 RISC-V 的公司，但它是最有代表性的商用 CPU IP 廠商之一。這件事很重要。因為它的產品表現，會直接影響外界怎麼看 RISC-V 能不能打進高效能市場。\u003C\u002Fp>\n\u003Cfigure class=\"my-6\">\u003Cimg src=\"https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1779150242176-okhu.png\" alt=\"SiFive 推出第三代 P550 與 P570 核心\" class=\"rounded-xl w-full\" loading=\"lazy\" \u002F>\u003C\u002Ffigure>\n\u003Cp>如果只看口號，大家都能說自己很開放。真正難的是，能不能把效能、功耗、面積和軟體支援一起做好。晶片設計不是選邊站，是在算帳。\u003C\u002Fp>\u003Cp>這也是為\u003Ca href=\"\u002Fnews\u002Fwhy-rust-community-threads-still-matter-zh\">什麼\u003C\u002Fa>第三代核心值得看。SiFive 不是只想證明「RISC-V 可以用」。它想證明「RISC-V 也能做高階 CPU IP，而且能進量產流程」。\u003C\u002Fp>\u003Cul>\u003Cli>\u003Ca href=\"https:\u002F\u002Fwww.arm.com\" target=\"_blank\" rel=\"noopener\">Arm\u003C\u002Fa> 仍是手機和大量嵌入式設計主力。\u003C\u002Fli>\u003Cli>\u003Ca href=\"https:\u002F\u002Fwww.intel.com\" target=\"_blank\" rel=\"noopener\">Intel\u003C\u002Fa> 與 \u003Ca href=\"https:\u002F\u002Fwww.amd.com\" target=\"_blank\" rel=\"noopener\">AMD\u003C\u002Fa> 仍主導 x86 生態。\u003C\u002Fli>\u003Cli>\u003Ca href=\"https:\u002F\u002Fwww.sifive.com\" target=\"_blank\" rel=\"noopener\">SiFive\u003C\u002Fa> 想把 RISC-V 變成高階客製晶片的實用選項。\u003C\u002Fli>\u003Cli>\u003Ca href=\"https:\u002F\u002Friscv.org\" target=\"_blank\" rel=\"noopener\">RISC-V International\u003C\u002Fa> 也持續擴大 ISA 生態。\u003C\u002Fli>\u003C\u002Ful>\u003Cp>這種競爭對買家是好事。選項多，議價空間就大。你也比較不會被單一供應商綁死。對整個產業來說，這代表 RISC-V 已經不是旁支路線，而是有商業壓力在推的主題。\u003C\u002Fp>\u003Ch2>哪些數字和訊號最該盯\u003C\u002Fh2>\u003Cp>這次最可惜的是，SiFive 沒有公開完整 benchmark。沒有數字，就很難直接跟 ARM Cortex 或其他 RISC-V 核心硬碰硬。這會讓外界先保留一點態度。\u003C\u002Fp>\u003Cp>但你還是能從公開資訊看出幾個重點。首先是第三代。其次是 P570 的 out-of-order 定位。再來是它明講效率。這三個訊號放在一起，意思很清楚，就是想打更高階的設計案。\u003C\u002Fp>\u003Cp>如果後續有客戶晶片出來，才是真正的考試。到那時候，大家才會看它在真實工作負載下，能不能在效能、功耗和面積三者之間站穩。\u003C\u002Fp>\u003Cul>\u003Cli>第三代 Performance IP：代表核心架構已經進入更成熟的版本。\u003C\u002Fli>\u003Cli>out-of-order：代表目標不是超低階，而是更吃資源的 CPU 工作。\u003C\u002Fli>\u003Cli>缺少 benchmark：代表目前還不能直接和競品硬比。\u003C\u002Fli>\u003Cli>後續 design win：會比發表稿更有判斷價值。\u003C\u002Fli>\u003C\u002Ful>\u003Ch2>RISC-V 產業脈絡其實很現實\u003C\u002Fh2>\u003Cp>很多人談 RISC-V，喜歡只談理想。開放、社群、自由授權，這些都沒錯。但晶片產業最後看的還是成本、時程和風險。沒有軟體支援，硬體再漂亮也只是 demo。\u003C\u002Fp>\u003Cp>所以 SiFive 這類公司很像橋樑。它把開放 ISA 變成可交付的 CPU IP。對不少晶片公司來說，這比從零寫核心更省時間，也更符合商業節奏。\u003C\u002Fp>\u003Cp>我自己的判斷很直接。RISC-V 真正往上走，不是靠一次發表。是靠一批實際出貨的晶片。只要第三代 P550 和 P570 能進到更多設計案，市場就會更認真看待它。\u003C\u002Fp>\u003Ch2>接下來該看什麼\u003C\u002Fh2>\u003Cp>接下來最重要的不是再聽一次口號，而是等更實際的資料。像是效能數字、功耗數字、面積數字，還有軟體工具鏈支援。這些才是工程師會拿來做決策的東西。\u003C\u002Fp>\u003Cp>如果 SiFive 真的把第三代核心做穩，下一步應該會出現更多採用案例。那時候，RISC-V 在高效能市場的存在感才會更明確。你如果在做晶片選型，這條線現在值得追。\u003C\u002Fp>\u003Cp>我的建議很簡單。先把這次發表當成訊號，不要當成結論。等後續 benchmark 和 design win 出來，再來判斷它到底是宣傳，還是真的能打。\u003C\u002Fp>","SiFive 發表第三代 P550 與 P570 RISC-V 核心，主打高效能設計與 out-of-order 架構，想把 RISC-V 推進更高階的晶片市場。","www.businesswire.com","https:\u002F\u002Fwww.businesswire.com\u002Fnews\u002Fhome\u002F20260512596781\u002Fen\u002FSiFive-Sets-New-Bar-for-High-Performance-RISC-V-with-Third-Generation-Performance-P550-and-P570-IP",null,"https:\u002F\u002Fxxdpdyhzhpamafnrdkyq.supabase.co\u002Fstorage\u002Fv1\u002Fobject\u002Fpublic\u002Fcovers\u002Finline-1779150236307-rv7h.png","model-release","zh","8b0922ab-5453-4b2f-9cf7-4937d844521a",[17,18,19,20,21,22,23,24],"SiFive","RISC-V","P550","P570","out-of-order","CPU核心","晶片設計","高效能運算",[26,27,28],"SiFive 推出第三代 P550 與 P570 Performance 核心，重點放在高效能 RISC-V 設計。","P570 Gen 3 主打 out-of-order 架構，目標是更高階的 CPU 工作負載。","這次沒有公開完整 benchmark，後續 design win 和實測數字才是關鍵。",5,"2026-05-19T00:23:34.274317+00:00","2026-05-19T00:23:34.213+00:00","0ccb5d2e-69f1-4354-a3e0-cb370221cd95",{"tags":34,"relatedLang":44,"relatedPosts":48},[35,37,39,40,42],{"name":17,"slug":36},"sifive",{"name":19,"slug":38},"p550",{"name":21,"slug":21},{"name":18,"slug":41},"risc-v",{"name":20,"slug":43},"p570",{"id":15,"slug":45,"title":46,"language":47},"sifive-third-gen-p550-p570-risc-v-cores-en","SiFive launches third-gen P550 and P570 cores","en",[49,55,61,67,73,79],{"id":50,"slug":51,"title":52,"cover_image":53,"image_url":53,"created_at":54,"category":13},"1985ce38-03c6-4968-96fa-b751553bbef3","why-claude-opus-48-is-not-the-big-story-zh","為什麼 Claude Opus 4.8 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