IIT Madras will host DIR-V 2026 in Chennai

IIT Madras will host DIR-V 2026 in Chennai on August 1-2.

IIT Madras is bringing its third Digital India RISC-V symposium to the IIT Madras Research Park on August 1-2, 2026. The event is built around one blunt idea: India wants more control over the chips that power its digital economy, and open instruction-set design is part of that plan.

What IIT Madras is trying to build

The symposium is more than a conference with a chip-shaped theme. It is a meeting point for policymakers, researchers, startups, investors, faculty members, students, and industry leaders who are working on processor design, embedded systems, AI hardware, and cybersecurity.

That mix matters because semiconductor work in India has often been fragmented. Universities produce talent, startups prototype ideas, and government programs fund strategic capacity, but those groups do not always sit in the same room. DIR-V is trying to compress that distance.

MeitY is one of the partners, alongside RISC-V International, which maintains the open-standard RISC-V instruction set architecture. For India, that matters because open standards lower dependence on a single vendor’s chip roadmap.

• Third edition of the symposium
• Two-day format in Chennai
• Theme: “Empowering Bharat’s Semiconductor Future”
• Focus areas include processor design and AI hardware

Why RISC-V keeps showing up in India’s chip plans

RISC-V is an instruction set architecture, which is the rulebook a processor follows to execute code. Unlike proprietary architectures, it is open and extensible, which makes it attractive for research labs, startups, and national chip programs that want more design freedom.

India has been talking for years about building deeper semiconductor capacity, but the real bottleneck is not just fabrication. It is design talent, toolchains, verification, system integration, and the ability to turn ideas into products. That is where an event like DIR-V can do practical work.

“As India’s digital economy expands, secure and trusted semiconductor technologies have become a strategic national priority,” said V. Kamakoti, Director of IIT Madras.

Kamakoti’s comment gets to the point better than any brochure could. India does not need chip talk for its own sake; it needs chips that can be designed, audited, adapted, and shipped in a way that fits local strategic needs.

The symposium also gives startups and labs a stage for live demos. That is important because semiconductor conversations can get abstract fast. A working processor board, an embedded system demo, or a security prototype tells you more than a hundred slides about where a team actually is.

What the event says about India’s chip strategy

The guest list tells the story. When policymakers, global technology experts, and industry leaders gather around an open ISA, the discussion is no longer about whether India should care about chip design. It is about which parts of the stack India can influence now.

That stack includes architecture choices, IP reuse, verification, manufacturing partnerships, and the software that runs on top. RISC-V is useful here because it lets teams experiment without asking permission from a closed platform owner.

• Open ISA: RISC-V
• Institutional host: IIT Madras
• Government partner: MeitY
• International standards body: RISC-V International
• Venue city: Chennai

There is also a talent angle that is easy to miss. Students and faculty members get direct exposure to the same people shaping India’s chip policy and product roadmaps. That kind of proximity can shorten the path from academic work to startup formation or industrial deployment.

For readers tracking India’s broader tech policy, this symposium fits the same arc as other homegrown compute efforts, including processor research, secure hardware, and public-sector support for strategic technology. If you want a related read, see our coverage of India’s chip design push.

What to watch on August 1-2

The most useful signals will not come from panel titles. They will come from the demos, the startup exhibits, and who shows up to talk about deployment rather than theory. If the event produces concrete collaborations between academia and industry, that will matter more than the usual event recap.

It will also be worth watching whether the conversation stays centered on open silicon design, or broadens into procurement, manufacturing, and export-ready product paths. India has already shown it can host ambitious tech policy events; the harder part is turning them into repeatable execution.

DIR-V 2026 gives India a rare chance to connect policy language with engineering reality. If the symposium produces even a handful of serious design partnerships, the bigger question becomes simple: which Indian chips will move from conference demo to commercial product first?